6111 search results - page 163 / 1223 » Time, Hardware, and Uniformity |
CHARME
1993
Springer
14 years 2 months ago
1993
Springer
To perform veri cation of digital systems with time bounded delays, it is essential to characterize the space of all possible system behaviors. In this paper, we describe our analy...
ASPDAC
2006
ACM
14 years 2 months ago
2006
ACM
- We propose a framework to unify the process of false paths and multi-cycle paths in static timing analysis (STA). We use subgraphs attached with timing constraints to represent f...
ICCAD
2004
IEEE
14 years 7 months ago
2004
IEEE
Abstract— This paper presents a post-route, timingconstrained gate-sizing algorithm for crosstalk reduction. Gate-sizing has emerged as a practical and feasible method to reduce ...
ICECCS
2005
IEEE
14 years 4 months ago
2005
IEEE
When designing a complex system, Object-Z is a powerful logic-based language for modeling the system state aspects, and Timed Automata is an excellent graph-based notation for cap...
ICCD
2003
IEEE
14 years 3 months ago
2003
IEEE
We present a test scheduling methodology for core-based system-on-chips that allows tradeoff between system power dissipation and overall test time. The basic strategy is to use t...