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FPL
2006
Springer
103views Hardware» more  FPL 2006»
14 years 2 months ago
A System Design Methodology for Reducing System Integration Time and Facilitating Modular Design Verification
This paper provides a realistic case study of using the previously introduced SIMPPL system architectural model, which fixes the physical interface and communication protocols bet...
Lesley Shannon, Blair Fort, Samir Parikh, Arun Pat...
CAV
2003
Springer
155views Hardware» more  CAV 2003»
14 years 2 months ago
An Improved On-The-Fly Tableau Construction for a Real-Time Temporal Logic
Abstract. Temporal logic is popular for specifying correctness properties of reactive systems. Real-time temporal logics add the ability to express quantitative timing aspects. Tab...
Marc Geilen
ICCAD
1995
IEEE
106views Hardware» more  ICCAD 1995»
14 years 2 months ago
Re-engineering of timing constrained placements for regular architectures
In a typical design ow, the design may be altered slightly several times after the initial design cycle according to minor changes in the design speci cation either as a result o...
Anmol Mathur, K. C. Chen, C. L. Liu
COMPSYSTECH
2010
13 years 7 months ago
Integration of neural networks and expert systems for time series prediction
: In this paper an approach for development of univariate time series prediction library in Java and its integration with an existing CLIPS related system is presented .A backpropa...
Ventsislav Nikolov, Valeri Bogdanov
ASPDAC
2012
ACM
241views Hardware» more  ASPDAC 2012»
12 years 6 months ago
On error modeling of electrical bugs for post-silicon timing validation
—There is great demand for an accurate and scalable metric to evaluate the functional stimuli, testbench checkers, and DfD (Design-for-Debug) structures used in post-silicon timi...
Ming Gao, Peter Lisherness, Kwang-Ting Cheng, Jing...