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VLSID
2003
IEEE
147views VLSI» more  VLSID 2003»
14 years 9 months ago
SoC Synthesis with Automatic Hardware Software Interface Generation
Design of efficient System-on-Chips (SoCs) require thorough application analysis to identify various compute intensive parts. These compute intensive parts can be mapped to hardwa...
Amarjeet Singh 0002, Amit Chhabra, Anup Gangwar, B...
ICCD
2007
IEEE
322views Hardware» more  ICCD 2007»
14 years 5 months ago
Voltage drop reduction for on-chip power delivery considering leakage current variations
In this paper, we propose a novel on-chip voltage drop reduction technique for on-chip power delivery networks of VLSI systems in the presence of variational leakage current sourc...
Jeffrey Fan, Ning Mi, Sheldon X.-D. Tan
CGO
2010
IEEE
14 years 3 months ago
Integrated instruction selection and register allocation for compact code generation exploiting freeform mixing of 16- and 32-bi
For memory constrained embedded systems code size is at least as important as performance. One way of increasing code density is to exploit compact instruction formats, e.g. ARM T...
Tobias J. K. Edler von Koch, Igor Böhm, Bj&ou...
MSWIM
2009
ACM
14 years 3 months ago
Designing an asynchronous group communication middleware for wireless users
We evaluate an asynchronous gossiping middleware for wireless users that propagates messages from any group member to all the other group members. This propagation can either be i...
Xuwen Yu, Surendar Chandra
CLUSTER
2009
IEEE
14 years 3 months ago
MDCSim: A multi-tier data center simulation, platform
Abstract—Performance and power issues are becoming increasingly important in the design of large cluster based multitier data centers for supporting a multitude of services. Desi...
Seung-Hwan Lim, Bikash Sharma, Gunwoo Nam, Eun-Kyo...