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» Time Equations for Lazy Functional (Logic) Languages
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FPGA
1997
ACM
118views FPGA» more  FPGA 1997»
14 years 1 months ago
Module Generation of Complex Macros for Logic-Emulation Applications
Logic emulation is a technique that uses dynamically reprogrammable systems for prototyping and design veri cation. Using an emulator, designers can realize designs through a soft...
Wen-Jong Fang, Allen C.-H. Wu, Duan-Ping Chen
JISBD
2000
13 years 10 months ago
Databases and Natural Language Interfaces
A Natural Language Interface for Databases allows users of multimedia kiosks to formulate natural language questions. User questions are first translated into a logic language and ...
Porfírio P. Filipe, Nuno J. Mamede
FORTE
2009
13 years 6 months ago
Keep It Small, Keep It Real: Efficient Run-Time Verification of Web Service Compositions
Abstract. Service compositions leverage remote services to deliver addedvalue distributed applications. Since services are administered and run by independent parties, the governan...
Luciano Baresi, Domenico Bianculli, Sam Guinea, Pa...
DAC
2003
ACM
14 years 10 months ago
Automatic trace analysis for logic of constraints
Verification of system designs continues to be a major challenge today. Simulation remains the primary tool for making sure that implementations perform as they should. We present...
Xi Chen, Harry Hsieh, Felice Balarin, Yosinori Wat...
KBSE
2005
IEEE
14 years 2 months ago
Learning to verify branching time properties
We present a new model checking algorithm for verifying computation tree logic (CTL) properties. Our technique is based on using language inference to learn the fixpoints necessar...
Abhay Vardhan, Mahesh Viswanathan