Sciweavers

652 search results - page 115 / 131
» Time Management in The High Level Architecture
Sort
View
DAC
2001
ACM
14 years 8 months ago
Latency-Driven Design of Multi-Purpose Systems-On-Chip
Milenko Drinic UCLA Computer Science Dep. 4732 Boelter Hall Los Angeles, CA 90095-1596 milenko@cs.ucla.edu Darko Kirovski Microsoft Research One Microsoft Way Redmond, WA 98052 da...
Seapahn Meguerdichian, Milenko Drinic, Darko Kirov...
MICRO
2009
IEEE
134views Hardware» more  MICRO 2009»
14 years 2 months ago
A case for dynamic frequency tuning in on-chip networks
Performance and power are the first order design metrics for Network-on-Chips (NoCs) that have become the de-facto standard in providing scalable communication backbones for mult...
Asit K. Mishra, Reetuparna Das, Soumya Eachempati,...
IMC
2007
ACM
13 years 9 months ago
An active measurement system for shared environments
Testbeds composed of end hosts deployed across the Internet enable researchers to simultaneously conduct a wide variety of experiments. Active measurement studies of Internet path...
Joel Sommers, Paul Barford
ENVSOFT
2007
78views more  ENVSOFT 2007»
13 years 7 months ago
CREDOS: A Conservation Reserve Evaluation And Design Optimisation System
A number of spatial decision support systems (SDSSs) are already available for the systematic planning of conservation reserves. These existing systems offer varying levels of int...
Neville D. Crossman, Lyall M. Perry, Brett A. Brya...
VLSID
2007
IEEE
210views VLSI» more  VLSID 2007»
14 years 7 months ago
Dynamically Optimizing FPGA Applications by Monitoring Temperature and Workloads
In the past, Field Programmable Gate Array (FPGA) circuits only contained a limited amount of logic and operated at a low frequency. Few applications running on FPGAs consumed exc...
Phillip H. Jones, Young H. Cho, John W. Lockwood