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» Time Management in The High Level Architecture
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VLSID
2002
IEEE
102views VLSI» more  VLSID 2002»
14 years 9 months ago
Losses in Multilevel Crossover in VLSI Interconnects
The radiation and surface wave losses may give rise to electromagnetic interference (EMI) problems in high speed VLSI interconnects. Over and above there will be dielectric and co...
P. K. Datta, S. Sanyal, D. Bhattacharya
ASPLOS
2004
ACM
14 years 2 months ago
Continual flow pipelines
Increased integration in the form of multiple processor cores on a single die, relatively constant die sizes, shrinking power envelopes, and emerging applications create a new cha...
Srikanth T. Srinivasan, Ravi Rajwar, Haitham Akkar...
CIDR
2003
150views Algorithms» more  CIDR 2003»
13 years 10 months ago
The Database Machine: Old Story, New Slant?
Current database management system technology is not well equipped to provide adequate support for what has been deemed the 3rd wave of computing -- Ubiquitous Computing. Such app...
Julie A. McCann
SIGMETRICS
2010
ACM
162views Hardware» more  SIGMETRICS 2010»
14 years 1 months ago
Coordinated power management of voltage islands in CMPs
Multiple clock domain architectures have recently been proposed to alleviate the power problem in CMPs by having different frequency/voltage values assigned to each domain based o...
Asit K. Mishra, Shekhar Srikantaiah, Mahmut T. Kan...
CLUSTER
2007
IEEE
14 years 3 months ago
Balancing productivity and performance on the cell broadband engine
— The Cell Broadband Engine (BE) is a heterogeneous multicore processor, combining a general-purpose POWER architecture core with eight independent single-instructionmultiple-dat...
Sadaf R. Alam, Jeremy S. Meredith, Jeffrey S. Vett...