— Architectural resources and program recurrences are the main limitations to the amount of Instruction-Level Parallelism (ILP) exploitable from loops, the most time-consuming pa...
The high transistor density afforded by modern VLSI processes have enabled the design of embedded processors that use clustered execution units to deliver high levels of performan...
In this paper, we describe two new algorithms for datapath scheduling which aim at energy reduction while maintaining performance. The proposed algorithms, time constrained and re...
High-Level Synthesis (HLS) is the field of transforming a high-level programming language, such as C, into a register transfer level(RTL) description of the design. In HLS, Binary...
It is widely known that parallel operation execution in multiprocessor systems generates a respective increase in memory accesses. Since the memory and bus subsystems provide a li...
Grigoris Dimitroulakos, Michalis D. Galanis, Costa...