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ICCAD
2000
IEEE
91views Hardware» more  ICCAD 2000»
14 years 1 months ago
A Timing-Constrained Algorithm for Simultaneous Global Routing of Multiple Nets
In this paper, we propose a new approach for VLSI interconnect global routing that can optimize both congestion and delay, which are often competing objectives. Our approach provi...
Jiang Hu, Sachin S. Sapatnekar
APIN
2006
207views more  APIN 2006»
13 years 9 months ago
Multi-Objective Genetic Algorithms for Vehicle Routing Problem with Time Windows
The Vehicle Routing Problem with Time windows (VRPTW) is an extension of the capacity constrained Vehicle Routing Problem (VRP). The VRPTW is NP-Complete and instances with 100 cus...
Beatrice M. Ombuki, Brian Ross, Franklin Hanshar
DM
2002
104views more  DM 2002»
13 years 8 months ago
A polynomial time algorithm for determining zero Euler-Petrie genus of an Eulerian graph
A dual-eulerian graph is a plane graph which has an ordering defined on its edge set which forms simultaneously an Euler circuit in the graph and an euler circuit in the dual grap...
Brigitte Servatius, Herman Servatius
CORR
2010
Springer
114views Education» more  CORR 2010»
13 years 6 months ago
On the Impact of Mutation-Selection Balance on the Runtime of Evolutionary Algorithms
The interplay between the mutation operator and the selection mechanism plays a fundamental role in the behaviour of evolutionary algorithms (EAs). However, this interplay is stil...
Per Kristian Lehre, Xin Yao
DAC
2009
ACM
14 years 9 months ago
A fully polynomial time approximation scheme for timing driven minimum cost buffer insertion
As VLSI technology enters the nanoscale regime, interconnect delay has become the bottleneck of the circuit timing. As one of the most powerful techniques for interconnect optimiz...
Shiyan Hu, Zhuo Li, Charles J. Alpert