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CJ
2006
84views more  CJ 2006»
15 years 5 months ago
Instruction Level Parallelism through Microthreading - A Scalable Approach to Chip Multiprocessors
Most microprocessor chips today use an out-of-order instruction execution mechanism. This mechanism allows superscalar processors to extract reasonably high levels of instruction ...
Kostas Bousias, Nabil Hasasneh, Chris R. Jesshope
ICIW
2009
IEEE
16 years 12 days ago
QoSMap: Achieving Quality and Resilience through Overlay Construction
We describe QoSMap, an overlay construction mechanism which computes high quality overlay networks for applications having stringent constraints on hop-degrading QoS metrics and p...
Jawwad Shamsi, Monica Brockmeyer
CODES
2003
IEEE
15 years 11 months ago
A modular simulation framework for architectural exploration of on-chip interconnection networks
Ever increasing complexity and heterogeneity of SoC platforms require diversified on-chip communication schemes beyond the currently omnipresent shared bus architectures. To prev...
Tim Kogel, Malte Doerper, Andreas Wieferink, Raine...
SECON
2008
IEEE
16 years 3 days ago
Adaptive Radio Modes in Sensor Networks: How Deep to Sleep?
—Energy-efficient performance is a central challenge in sensor network deployments, and the radio is a major contributor to overall energy node consumption. Current energyeffic...
Raja Jurdak, Antonio G. Ruzzelli, Gregory M. P. O'...
EPEW
2007
Springer
15 years 9 months ago
An Efficient Counter-Based Broadcast Scheme for Mobile Ad Hoc Networks
In mobile ad hoc networks (MANETs), broadcasting plays a fundamental role, diffusing a message from a given source node to all the other nodes in the network. Flooding is the simpl...
Aminu Mohammed, Mohamed Ould-Khaoua, Lewis M. Mack...