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IJCAI
1989
13 years 9 months ago
Neural Computing on a One Dimensional SIMD Array
Parallel processors offer a very attractive mechanism for the implementation of large neural networks. Problems in the usage of parallel processing in neural computing involve the...
Stephen S. Wilson
ICS
2009
Tsinghua U.
14 years 1 months ago
Dynamic task set partitioning based on balancing memory requirements to reduce power consumption
ABSTRACT Because of technology advances power consumption has emerged up as an important design issue in modern high-performance microprocessors. As a consequence, research on redu...
Diana Bautista, Julio Sahuquillo, Houcine Hassan, ...
BICA
2010
13 years 3 months ago
Modelling Human Memory in Robotic Companions for Personalisation and Long-term Adaptation in HRI
This paper investigates issues of robot's personalization and long-term adaptation in human-robot interaction (HRI). It demonstrates the design and first technical implementat...
Wan Ching Ho, Kerstin Dautenhahn, Mei Yii Lim, Kyr...
CODES
2007
IEEE
14 years 2 months ago
Predator: a predictable SDRAM memory controller
Memory requirements of intellectual property components (IP) in contemporary multi-processor systems-on-chip are increasing. Large high-speed external memories, such as DDR2 SDRAM...
Benny Akesson, Kees Goossens, Markus Ringhofer
ICC
2007
IEEE
14 years 2 months ago
Computing Maximum-Likelihood Bounds for Reed-Solomon Codes over Partial Response Channels
Abstract—Computing maximum-likelihood bounds on the performance of systems involving partial response (PR) channels, with or without an error correcting code present, is rather c...
Richard M. Todd, J. R. Cruz