769 search results - page 125 / 154 » Timed Circuit Synthesis Using Implicit Methods |
WWW
2007
ACM
14 years 8 months ago
2007
ACM
Discovering mappings between concept hierarchies is widely regarded as one of the hardest and most urgent problems facing the Semantic Web. The problem is even harder in domains w...
FMCAD
2004
Springer
14 years 1 months ago
2004
Springer
Most symbolic model checkers are based on either Binary Decision Diagrams (BDDs), which may grow exponentially large, or Satisfiability (SAT) solvers, whose time requirements rapi...
ASPDAC
2005
ACM
13 years 9 months ago
2005
ACM
- This paper presents a novel approach for fast transient analysis of buffered hybrid structured clock networks. The new method applies structure reduction and relaxed hierarchical...
ARVLSI
1999
IEEE
14 years 5 hour ago
1999
IEEE
We describe a method to clock the domino pipeline at the maximum rate by using soft synchronizers between pipeline stages and thus allowing "time borrowing," i.e., allow...
VLSID
2002
IEEE
14 years 8 months ago
2002
IEEE
Interconnect delay has become a critical factor in determining the performance of integrated circuits. Routing and buffering are powerful means of improving the circuit speed and ...