769 search results - page 12 / 154 » Timed Circuit Synthesis Using Implicit Methods |
ICCAD
2008
IEEE
14 years 4 months ago
2008
IEEE
We propose a post-placement physical synthesis algorithm that can apply multiple circuit synthesis and placement transforms on a placed circuit to improve the critical path delay ...
EURODAC
1994
IEEE
13 years 11 months ago
1994
IEEE
payload. The current recommendations include SDH as the physical layer transmission standard. It is defined the BISDN user network interface (UNI) SDH-based at 155.52 Mbit/s, but t...
EURODAC
1994
IEEE
13 years 11 months ago
1994
IEEE
An approach for stuck-at-i and delay-fault testing of redundant circuits without modifying the logic is proposed. The only requirement is the ability to control both phases of eac...
ASPDAC
2009
ACM
14 years 2 months ago
2009
ACM
—Reversible logic studies have promising potential on energy lossless circuit design, quantum computation, nanotechnology, etc. Reversible logic features a one-to-one input outpu...
ASPDAC
2001
ACM
13 years 11 months ago
2001
ACM
Abstract-- In order to continue to produce circuits of increasing speeds, designers must consider aggressive circuit design styles such as self-resetting or delayed-reset domino ci...