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» Timed Circuit Synthesis Using Implicit Methods
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DAC
2004
ACM
14 years 8 months ago
Efficient on-line testing of FPGAs with provable diagnosabilities
We present novel and efficient methods for on-line testing in FPGAs. The testing approach uses a ROving TEster (ROTE), which has provable diagnosabilities and is also faster than ...
Vinay Verma, Shantanu Dutt, Vishal Suthar
JUCS
2007
95views more  JUCS 2007»
13 years 7 months ago
Using Place Invariants and Test Point Placement to Isolate Faults in Discrete Event Systems
: This paper describes a method of using Petri net P-invariants in system diagnosis. To model this process a net oriented fault classification is presented. Hence, the considered d...
Iwan Tabakow
MEMOCODE
2006
IEEE
14 years 1 months ago
Latency-insensitive design and central repetitive scheduling
The theory of latency-insensitive design (LID) was recently invented to cope with the time closure problem in otherwise synchronous circuits and programs. The idea is to allow the...
Julien Boucaron, Robert de Simone, Jean-Vivien Mil...
DAC
2003
ACM
14 years 8 months ago
Partial task assignment of task graphs under heterogeneous resource constraints
This paper presents a novel partial assignment technique (PAT) that decides which tasks should be assigned to the same resource without explicitly defining assignment of these tas...
Radoslaw Szymanek, Krzysztof Kuchcinski
ICPPW
2002
IEEE
14 years 18 days ago
Hebbian Algorithms for a Digital Library Recommendation System
generally meta-data, so that documents on any specific subject can be transparently retrieved. While quality control can in principle still rely on the traditional methods of peer-...
Francis Heylighen, Johan Bollen