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» Timed Circuit Synthesis Using Implicit Methods
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DAC
2006
ACM
14 years 11 months ago
Generation of yield-aware Pareto surfaces for hierarchical circuit design space exploration
Pareto surfaces in the performance space determine the range of feasible performance values for a circuit topology in a given technology. We present a non-dominated sorting based ...
Saurabh K. Tiwary, Pragati K. Tiwary, Rob A. Ruten...
ASPDAC
2006
ACM
130views Hardware» more  ASPDAC 2006»
14 years 4 months ago
Convergence-provable statistical timing analysis with level-sensitive latches and feedback loops
Statistical timing analysis has been widely applied to predict the timing yield of VLSI circuits when process variations become significant. Existing statistical latch timing met...
Lizheng Zhang, Jeng-Liang Tsai, Weijen Chen, Yuhen...
DAC
2007
ACM
14 years 2 months ago
Integrated Droplet Routing in the Synthesis of Microfluidic Biochips
Microfluidic biochips are revolutionizing many areas of biochemistry and biomedical sciences. Several synthesis tools have recently been proposed for the automated design of bioch...
Tao Xu, Krishnendu Chakrabarty
ICCAD
2006
IEEE
101views Hardware» more  ICCAD 2006»
14 years 7 months ago
A unified non-rectangular device and circuit simulation model for timing and power
— For 65nm and below devices, even after optical proximity correction (OPC), the gate may still be non-rectangular. There are several limited works on the device and circuit char...
Sean X. Shi, Peng Yu, David Z. Pan
DAGSTUHL
2010
13 years 11 months ago
CSG Operations of Arbitrary Primitives with Interval Arithmetic and Real-Time Ray Casting
We apply Knoll et al.'s algorithm [9] to interactively ray-cast constructive solid geometry (CSG) objects of arbitrary primitives represented as implicit functions. Whereas m...
Younis Hijazi, Aaron Knoll, Mathias Schott, Andrew...