Generation of yield-aware Pareto surfaces for hierarchical circuit design space exploration

Pareto surfaces in the performance space determine the range of feasible performance values for a circuit topology in a given technology. We present a non-dominated sorting based global optimization algorithm to generate the nominal pareto front efficiently using a simulator-in-a-loop approach. The solutions on this pareto front combined with efficient Monte Carlo approximation ideas are then used to compute the yield-aware pareto fronts. We show experimental results for both the nominal and yield-aware pareto fronts for power and phase noise for a voltage controlled oscillator (VCO) circuit. The presented methodology computes yield-aware pareto fronts in approximately 5-6 times the time required for a single circuit synthesis run and is thus practically efficient. We also show applications of yield-aware paretos to find the optimal VCO circuit to meet the system level specifications of a phase locked loop. Categories and Subject Descriptors B.7.2 [Integrated Circuits]: Design Aids Ge...

• Type: Conference
• Year: 2006
• Where: DAC
• Authors: Saurabh K. Tiwary, Pragati K. Tiwary, Rob A. Rutenbar
• Keywords: Computes Yield-aware Pareto, DAC 2006, Design Automation, Nominal Pareto, Yield-aware Pareto Fronts