769 search results - page 46 / 154 » Timed Circuit Synthesis Using Implicit Methods |
ERSA
2009
13 years 8 months ago
2009
- The FPGA (re)configuration is a time-consuming process and a bottleneck in FPGA-based Run-Time Reconfigurable (RTR) systems. In this paper, we present a High Level Synthesis (HLS...
ICCAD
1997
IEEE
14 years 2 months ago
1997
IEEE
A deductive technique is presented that uses voltage testing for the diagnosis of single bridging faults between two gate input or output lines and is applicable to combinational ...
VLSID
2005
IEEE
14 years 10 months ago
2005
IEEE
This paper employs general multivariate normal distribution to develop a new efficient statistical timing analysis methodology. The paper presents the theoretical framework of the...
ISPD
2005
ACM
14 years 3 months ago
2005
ACM
Placement is a critical component of today's physical synthesis flow with tremendous impact on the final performance of VLSI designs. However, it accounts for a significant p...
PATMOS
2007
Springer
14 years 4 months ago
2007
Springer
Abstract. The continuous miniaturization of semiconductor devices imposes serious threats to design robustness against process variations and environmental fluctuations. Modern ci...