769 search results - page 52 / 154 » Timed Circuit Synthesis Using Implicit Methods |
104
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DAC
1995
ACM
15 years 5 months ago
1995
ACM
Abstract— Many asynchronous designs are naturally specified and implemented hierarchically as an interconnection of separate asynchronous modules that operate concurrently and c...
101
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ISCAS
2007
IEEE
15 years 8 months ago
2007
IEEE
—A shared bus is a suitable structure for minimizing the interconnections costs in system synthesis. It has also been shown that the word-length of Functional Units has a great i...
109
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ICDCS
2007
IEEE
2007
IEEE
Exploiting Symbolic Techniques in Automated Synthesis of Distributed Programs with Large State Space
15 years 8 months ago
Automated formal analysis methods such as program verification and synthesis algorithms often suffer from time complexity of their decision procedures and also high space complex...
123
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FCCM
2005
IEEE
15 years 7 months ago
2005
IEEE
When designing systems-on-a-chip (SoCs), a unique opportunity exists to generate custom FPGA architectures that are specific to the application domain in which the device will be ...
134
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DAC
2008
ACM
15 years 4 months ago
2008
ACM
Clock skew scheduling has been traditionally considered as a tool for improving the clock period in a sequential circuit. Timing slack is "stolen" from fast combinationa...