769 search results - page 64 / 154 » Timed Circuit Synthesis Using Implicit Methods |
ISPD
2012
ACM
12 years 5 months ago
2012
ACM
In this paper, we propose a new approach for gated bus synthesis [16] with minimum wire capacitance per transaction in three-dimensional (3D) ICs. The 3D IC technology connects di...
ACSD
2003
IEEE
14 years 1 months ago
2003
IEEE
Abstract. The behaviour of asynchronous circuits is often described by Signal Transition Graphs (STGs), which are Petri nets whose transitions are interpreted as rising and falling...
ICCAD
2004
IEEE
14 years 7 months ago
2004
IEEE
—In this paper, we present a new block budgeting algorithm which speeds up timing closure in timing driven hierarchical flows. After a brief description of the addressed flow, ...
ISCAS
2003
IEEE
14 years 3 months ago
2003
IEEE
We present an equation-based transistor size optimizer that minimizes delay of custom circuits. Our method uses static timing analysis to find the critical paths and numerical met...
COLING
2010
13 years 5 months ago
2010
Temporal expressions in texts contain significant temporal information. Understanding temporal information is very useful in many NLP applications, such as information extraction,...