769 search results - page 71 / 154 » Timed Circuit Synthesis Using Implicit Methods |
DSD
2010
IEEE
13 years 8 months ago
2010
IEEE
— In this paper we propose a new method of test patterns compression based on a design of a dedicated SAT-based ATPG (Automatic Test Pattern Generator). This compression method i...
FORMATS
2006
Springer
14 years 1 months ago
2006
Springer
Networks of communicating finite-state machines equipped with local clocks generate timed MSCs. We consider the problem of checking whether these timed MSCs are "consistent&qu...
ICCAD
2006
IEEE
14 years 7 months ago
2006
IEEE
Most existing RCL−1 circuit reductions stamp inverse inductance L−1 elements by a second-order nodal analysis (NA). The NA formulation uses nodal voltage variables and describ...
DATE
1999
IEEE
14 years 2 months ago
1999
IEEE
Commonly used scheduling algorithms in high-level synthesis only accept one process at a time and are not capable of sharing resources across process boundaries. This results in t...
ASPDAC
2008
ACM
14 years 8 days ago
2008
ACM
In the nanometer manufacturing region, process variation causes significant uncertainty for circuit performance verification. Statistical static timing analysis (SSTA) is thus dev...