4306 search results - page 125 / 862 » Timed Testing with TorX |
ISQED
2003
IEEE
14 years 3 months ago
2003
IEEE
A structurally testable delay fault might become untestable in the functional mode of the circuit due to logic or timing constraints or both. Experimental data suggests that there...
HCI
2009
13 years 8 months ago
2009
The authors have developed a performance test, CPTOP2 (Cognitive Performance Test of Productivity), which consists of four task tests to evaluate cognitive abilities of office work...
VTS
2003
IEEE
14 years 3 months ago
2003
IEEE
In this paper, an efficient technique for test data volume reduction based on the shared scan-in (Illinois Scan) architecture and the scan chain reconfiguration (Dynamic Scan) arc...
SERA
2005
Springer
14 years 3 months ago
2005
Springer
In recent years, embedded systems have become so complex and the development time to market is required to be shorter than before. As embedded systems include more functions for n...
ICCAD
1995
IEEE
14 years 1 months ago
1995
IEEE
: We present several techniques for accelerating dynamic vector compaction for combinational and sequential circuits. A key feature of all our techniques is that they significantly...