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ETS
2006
IEEE
119views Hardware» more  ETS 2006»
14 years 4 months ago
On-Chip Test Generation Using Linear Subspaces
A central problem in built-in self test (BIST) is how to efficiently generate a small set of test vectors that detect all targeted faults. We propose a novel solution that uses l...
Ramashis Das, Igor L. Markov, John P. Hayes
DATE
2003
IEEE
96views Hardware» more  DATE 2003»
14 years 3 months ago
Test Data Compression: The System Integrator's Perspective
Test data compression (TDC) is a promising low-cost methodology for System-on-a-Chip (SOC) test. This is due to the fact that it can reduce not only the volume of test data but al...
Paul Theo Gonciari, Bashir M. Al-Hashimi, Nicola N...
KBSE
2003
IEEE
14 years 3 months ago
Automated Software Testing Using a Metaheuristic Technique Based on Tabu Search
The use of techniques for automating the generation of software test cases is very important as it can reduce the time and cost of this process. The latest methods for automatic g...
Eugenia Díaz, Javier Tuya, Raquel Blanco
TOOLS
2010
IEEE
14 years 3 months ago
Contract-Driven Testing of JavaScript Code
JSContest is a tool that enhances JavaScript with simple, type-like contracts and provides a framework for monitoring and guided random testing of programs against these contracts ...
Phillip Heidegger, Peter Thiemann
MTDT
2000
IEEE
137views Hardware» more  MTDT 2000»
14 years 2 months ago
Diagnostic Testing of Embedded Memories Based on Output Tracing
A new approach to diagnostic testing of embedded memories is presented which enables the design of tests that provide complete detection and distinguishing of all faults in a give...
Dirk Niggemeyer, Elizabeth M. Rudnick, Michael Red...