176 search results - page 14 / 36 » Timed Verification of Asynchronous Circuits |
DAC
2005
ACM
14 years 8 months ago
2005
ACM
Recent study shows that the existing first order canonical timing model is not sufficient to represent the dependency of the gate delay on the variation sources when processing an...
VLSID
1999
IEEE
13 years 12 months ago
1999
IEEE
This paper presents a detailed description of the application of a formal verification methodology to an ARM processor. The processor, a hybrid between the ARM7 and the StrongARM ...
ASYNC
2006
IEEE
14 years 1 months ago
2006
IEEE
A fast asynchronous shift register is used as the serializer and de-serializer in a novel bit-serial on-chip communication link. The link employs two-phase transition-based LEDR e...
DFT
2006
IEEE
13 years 11 months ago
2006
IEEE
The concept of clocking for QCA, referred to as the four-phase clocking, is widely used. However, inherited characteristics of QCA, such as the way to hold state, the way to synch...
ISCAS
2006
IEEE
14 years 1 months ago
2006
IEEE
— In this paper an architecture, signal reconstruction algorithm and first-ever implementation of an asynchronous delta-sigma converter are presented. The signal reconstruction ...