176 search results - page 15 / 36 » Timed Verification of Asynchronous Circuits |
ICCAD
2003
IEEE
14 years 4 months ago
2003
IEEE
Modeling frequency-dependent nonlinear characteristics of complex analog blocks and subsystems is critical for enabling efficient verification of mixed-signal system designs. Rece...
DDECS
2009
IEEE
14 years 2 months ago
2009
IEEE
—Quasi Delay Insensitive asynchronous logic is a very robust system allowing safe implementations while requiring minimal timing assumptions. Unfortunately the design methodologi...
ESANN
2008
13 years 9 months ago
2008
In this paper we present an original neighborhood mechanism for WTM self-organizing Kohonen map implemented in CMOS 0.18 m process. Proposed mechanism is an asynchronous circuit an...
VLSI
2007
Springer
14 years 1 months ago
2007
Springer
— Software simulation remains the most used method for VHDL RTL functional verification. The functional verification process essentially consists of two parts. The first one is t...
CORR
2010
Springer
13 years 6 months ago
2010
Springer
This paper discusses highly general mechanisms for specifying the refinement of a real-time system as a collection of lower level parallel components that preserve the timing and ...