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» Timed Verification of Asynchronous Circuits
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ASYNC
1997
IEEE
140views Hardware» more  ASYNC 1997»
13 years 11 months ago
The Design and Verification of A High-Performance Low-Control-Overhead Asynchronous Differential Equation Solver
Abstract-This paper describes the design and verification of a high-performance asynchronous differential equation solver benchmark circuit. The design has low control overhead whi...
Kenneth Y. Yun, Ayoob E. Dooply, Julio Arceo, Pete...
TCAD
2002
146views more  TCAD 2002»
13 years 7 months ago
Static scheduling of multidomain circuits for fast functional verification
With the advent of system-on-a-chip design, many application specific integrated circuits (ASICs) now require multiple design clocks that operate asynchronously to each other. This...
Murali Kudlugi, Russell Tessier
ATS
2001
IEEE
101views Hardware» more  ATS 2001»
13 years 11 months ago
Framework of Timed Trace Theoretic Verification Revisited
This paper develops a framework to support trace theoretic verification of timed circuits and systems. A theoretical foundation for classifying timed traces as either successes or...
Bin Zhou, Tomohiro Yoneda, Chris J. Myers
ASYNC
2007
IEEE
132views Hardware» more  ASYNC 2007»
14 years 2 months ago
Area Optimizations for Dual-Rail Circuits Using Relative-Timing Analysis
Future deep sub-micron technologies will be characterized by large parametric variations, which could make asynchronous design an attractive solution for use on large scale. Howev...
Tiberiu Chelcea, Girish Venkataramani, Seth Copen ...
ACSD
2006
IEEE
89views Hardware» more  ACSD 2006»
13 years 11 months ago
On process-algebraic verification of asynchronous circuits
Asynchronous circuits have received much attention recently due to their potential for energy savings. Process algebras have been extensively used in the modelling, analysis and sy...
Xu Wang, Marta Z. Kwiatkowska