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ISSTA
2004
ACM
14 years 1 months ago
Automating commutativity analysis at the design level
Two operations commute if executing them serially in either order results in the same change of state. In a system in which commands may be issued simultaneously by different use...
Greg Dennis, Robert Seater, Derek Rayside, Daniel ...
KR
1991
Springer
13 years 11 months ago
Meta-Reasoning in Executable Temporal Logic
Temporal logic can be used as a programming language. If temporal formulae are represented in the form of an implication where the antecedent refers to the past, and the consequen...
Howard Barringer, Michael Fisher, Dov M. Gabbay, A...
DFT
2003
IEEE
113views VLSI» more  DFT 2003»
14 years 28 days ago
Buffer and Controller Minimisation for Time-Constrained Testing of System-On-Chip
Test scheduling and Test Access Mechanism (TAM) design are two important tasks in the development of a System-on-Chip (SOC) test solution. Previous test scheduling techniques assu...
Anders Larsson, Erik Larsson, Petru Eles, Zebo Pen...
ATMOS
2007
114views Optimization» more  ATMOS 2007»
13 years 9 months ago
Fast Approaches to Robust Railway Timetabling
The Train Timetabling Problem (TTP) consists in finding a train schedule on a railway network that satisfies some operational constraints and maximizes a profit function which c...
Matteo Fischetti, Arrigo Zanette, Domenico Salvagn...
DAC
2003
ACM
14 years 8 months ago
Automatic trace analysis for logic of constraints
Verification of system designs continues to be a major challenge today. Simulation remains the primary tool for making sure that implementations perform as they should. We present...
Xi Chen, Harry Hsieh, Felice Balarin, Yosinori Wat...