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» Timing Driven Architectural Adaptation
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TVLSI
2008
164views more  TVLSI 2008»
13 years 9 months ago
Dynamically Configurable Bus Topologies for High-Performance On-Chip Communication
The on-chip communication architecture is a major determinant of overall performance in complex System-on-Chip (SoC) designs. Since the communication requirements of SoC components...
Krishna Sekar, Kanishka Lahiri, Anand Raghunathan,...
WWW
2003
ACM
14 years 10 months ago
StoryML: Enabling Distributed Interfaces for Interactive Media
This paper introduces an adaptive architecture for presenting interactive timed media onto distributed networked devices. The interactive presentation is documented in StoryML, an...
Jun Hu
DAC
2006
ACM
14 years 3 months ago
DyXY: a proximity congestion-aware deadlock-free dynamic routing method for network on chip
A novel routing algorithm, namely dynamic XY (DyXY) routing, is proposed for NoCs to provide adaptive routing and ensure deadlock-free and livelock-free routing at the same time. ...
Ming Li, Qing-An Zeng, Wen-Ben Jone
DAC
2009
ACM
14 years 11 months ago
Enabling adaptability through elastic clocks
Power and performance benefits of scaling are lost to worst case margins as uncertainty of device characteristics is increasing. Adaptive techniques can dynamically adjust the mar...
Emre Tuncer, Jordi Cortadella, Luciano Lavagno
DAC
2002
ACM
14 years 11 months ago
An energy saving strategy based on adaptive loop parallelization
In this paper, we evaluate an adaptive loop parallelization strategy (i.e., a strategy that allows each loop nest to execute using different number of processors if doing so is be...
Ismail Kadayif, Mahmut T. Kandemir, Mustafa Karak&...