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» Timing analysis in high-level synthesis
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ICCAD
1992
IEEE
93views Hardware» more  ICCAD 1992»
13 years 11 months ago
Timing analysis in high-level synthesis
This paper presents a comprehensive timing model for behavioral-level specifications and algorithms for timing analysis in high-level synthesis. It is based on a timing network wh...
Andreas Kuehlmann, Reinaldo A. Bergamaschi
VLSID
2003
IEEE
92views VLSI» more  VLSID 2003»
14 years 8 months ago
Energy Efficient Scheduling for Datapath Synthesis
In this paper, we describe two new algorithms for datapath scheduling which aim at energy reduction while maintaining performance. The proposed algorithms, time constrained and re...
Saraju P. Mohanty, N. Ranganathan
ECRTS
2004
IEEE
13 years 11 months ago
Static Determination of Probabilistic Execution Times
Most previous research done in probabilistic schedulability analysis assumes a known distribution of execution times for each task of a real-time application. This is however not ...
Laurent David, Isabelle Puaut
ICDM
2005
IEEE
189views Data Mining» more  ICDM 2005»
14 years 1 months ago
Integrating Hidden Markov Models and Spectral Analysis for Sensory Time Series Clustering
We present a novel approach for clustering sequences of multi-dimensional trajectory data obtained from a sensor network. The sensory time-series data present new challenges to da...
Jie Yin, Qiang Yang
ISSS
1999
IEEE
151views Hardware» more  ISSS 1999»
13 years 12 months ago
Optimized System Synthesis of Complex RT Level Building Blocks from Multirate Dataflow Graphs
In order to cope with the ever increasing complexity of todays application specific integrated circuits, a building block based design methodology is established. The system is co...
Jens Horstmannshoff, Heinrich Meyr