290 search results - page 26 / 58 » Timing analysis in high-level synthesis |
ICDCS
1995
IEEE
14 years 1 months ago
1995
IEEE
Tasks in a real-time application usually have several stringent timing, resource, and communication requirements. Designing a distributed computing system which can meet all these...
ICFEM
2007
Springer
14 years 4 months ago
2007
Springer
Simulink is popular in industry for modeling and simulating embedded systems. It is deficient to handle requirements of high-level assurance and timing analysis. Previously, we sh...
FPL
2007
Springer
14 years 4 months ago
2007
Springer
Today’s heterogeneous embedded systems combine components from different domains, such as software, analogue hardware and digital hardware. The design and implementation of thes...
ICCAD
2003
IEEE
14 years 7 months ago
2003
IEEE
Traditional RTL power optimization techniques commit transformations at the RTL based on the estimation of area, delay and power. However, because of inadequate power and delay in...
FPL
2004
Springer
14 years 3 months ago
2004
Springer
A previous study [1] demonstrates the advantages of replacing registers by FPGA embedded memories during the storage allocation phase of High-Level Synthesis. The trend in new FPGA...