Sciweavers

290 search results - page 32 / 58
» Timing analysis in high-level synthesis
Sort
View
FCCM
2011
IEEE
220views VLSI» more  FCCM 2011»
13 years 1 months ago
Reducing the Energy Cost of Irregular Code Bases in Soft Processor Systems
— This paper describes an architecture and FPGA synthesis toolchain for building specialized, energy-saving coprocessors called Irregular Code Energy Reducers (ICERs) for a wide ...
Manish Arora, Jack Sampson, Nathan Goulding-Hotta,...
RTAS
2009
IEEE
14 years 4 months ago
Real-Time Video Surveillance over IEEE 802.11 Mesh Networks
In recent years, there has been an increase in video surveillance systems in public and private environments due to a heightened sense of security. The next generation of surveill...
Arvind Kandhalu, Anthony Rowe, Ragunathan Rajkumar...
ECMDAFA
2005
Springer
236views Hardware» more  ECMDAFA 2005»
14 years 3 months ago
Model-Driven Architecture for Hard Real-Time Systems: From Platform Independent Models to Code
The model-driven software development for hard real-time systems promotes the usage of the platform independent model as major design artifact. It is used to develop the software l...
Sven Burmester, Holger Giese, Wilhelm Schäfer
DAC
2003
ACM
14 years 11 months ago
Death, taxes and failing chips
In the way they cope with variability, present-day methodologies are onerous, pessimistic and risky, all at the same time! Dealing with variability is an increasingly important as...
Chandu Visweswariah
ICSEA
2006
IEEE
14 years 4 months ago
Extracting Simulation Models from Complex Embedded Real-Time Systems
A modeling process is presented for extracting timingaccurate simulation models from complex embedded realtime systems. The process is supported by two complementary methods for t...
Johan Andersson, Joel Huselius, Christer Norstr&ou...