Death, taxes and failing chips

In the way they cope with variability, present-day methodologies are onerous, pessimistic and risky, all at the same time! Dealing with variability is an increasingly important aspect of highperformance digital integrated circuit design, and indispensable for first-time-right hardware and cutting-edge performance. This invited paper discusses the methodology, analysis, synthesis and modeling aspects of this problem. These aspects of the problem are compared and contrasted in the ASIC and custom (microprocessor) domains. This paper pays particular attention to statistical timing analysis and enumerates desirable attributes that would render such an analysis capability practical and accurate. Categories and Subject Descriptors B.7.2 [Hardware]: Integrated circuits--Design aids General Terms Algorithms, verification Keywords Statistical timing, parametric yield prediction, design methodology.

• Type: Conference
• Year: 2003
• Where: DAC
• Authors: Chandu Visweswariah
• Keywords: DAC 2003, Design Automation, Keywords Statistical Timing, Parametric Yield Prediction, Statistical Timing Analysis