290 search results - page 9 / 58 » Timing analysis in high-level synthesis |
DSD
2010
IEEE
13 years 5 months ago
2010
IEEE
Reconfigurable FPGA based Systems-on-Chip (SoC) architectures are increasingly becoming the preferred solution for implementing modern embedded systems, due to their flexible natur...
ASYNC
1997
IEEE
13 years 11 months ago
1997
IEEE
This paper presents new timing analysis algorithms for efficient state space exploration during timed circuit synthesis. Timed circuits are a class of asynchronous circuits that i...
CEC
2008
IEEE
14 years 2 months ago
2008
IEEE
— The high-level synthesis process involves three interdependent and NP-complete optimization problems: (i) the operation scheduling, (ii) the resource allocation, and (iii) the ...
ASPDAC
1995
ACM
13 years 11 months ago
1995
ACM
In this paper we describe, a powerful post-synthesis approach called reclocking, for performance improvement by minimizing the total execution time. By back annotating the wire del...
AUTOMATICA
2004
13 years 7 months ago
2004
This paper deals with feedback controller synthesis for timed event graphs in dioids, where the number of initial tokens and time delays are only known to belong to intervals. We ...