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FDTC
2009
Springer
126views Cryptology» more  FDTC 2009»
14 years 3 months ago
WDDL is Protected against Setup Time Violation Attacks
—In order to protect crypto-systems against side channel attacks various countermeasures have been implemented such as dual-rail logic or masking. Faults attacks are a powerful t...
Nidhal Selmane, Shivam Bhasin, Sylvain Guilley, Ta...
SPAA
2005
ACM
14 years 2 months ago
Parallelizing time with polynomial circuits
We study the problem of asymptotically reducing the runtime of serial computations with circuits of polynomial size. We give an algorithmic size-depth tradeoff for parallelizing ...
Ryan Williams
ASYNC
2002
IEEE
112views Hardware» more  ASYNC 2002»
14 years 1 months ago
A Negative-Overhead, Self-Timed Pipeline
This paper presents a novel variation of wave pipelining that we call “surfing.” In previous wave pipelined designs, timing uncertainty grows monotonically as events propagat...
Mark R. Greenstreet, Brian D. Winters
ISVLSI
2002
IEEE
129views VLSI» more  ISVLSI 2002»
14 years 1 months ago
Accelerating Retiming Under the Coupled-Edge Timing Model
Retiming has been shown to be a powerful technique for improving the performance of synchronous circuits. However, even though retiming algorithms of polynomial time complexity ha...
Ingmar Neumann, Kolja Sulimma, Wolfgang Kunz
ISQED
2007
IEEE
152views Hardware» more  ISQED 2007»
14 years 2 months ago
Variation Aware Timing Based Placement Using Fuzzy Programming
In nanometer regime, the effects of variations are having an increasing impact on the delay and power characteristics of devices as well as the yield of the circuit. Statistical t...
Venkataraman Mahalingam, N. Ranganathan