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» Timing driven power gating
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DATE
2008
IEEE
132views Hardware» more  DATE 2008»
14 years 3 months ago
Coarse-Grain MTCMOS Sleep Transistor Sizing Using Delay Budgeting
Power gating is one of the most effective techniques in reducing the standby leakage current of VLSI circuits. In this paper we introduce a new approach for sleep transistor sizin...
Ehsan Pakbaznia, Massoud Pedram
GLVLSI
2000
IEEE
85views VLSI» more  GLVLSI 2000»
14 years 1 months ago
Fast and accurate estimation of floorplans in logic/high-level synthesis
In many applications such as high-level synthesis (HLS) and logic synthesis and possibly engineering change order (ECO) we would like to get fast and accurate estimations of diffe...
Kia Bazargan, Abhishek Ranjan, Majid Sarrafzadeh
ISLPED
2010
ACM
153views Hardware» more  ISLPED 2010»
13 years 8 months ago
Leakage minimization using self sensing and thermal management
We have developed a system architecture, measuring and modeling techniques, and algorithms for on-line power and energy optimization and thermal management. The starting point for...
Alireza Vahdatpour, Miodrag Potkonjak
MICRO
2010
IEEE
145views Hardware» more  MICRO 2010»
13 years 6 months ago
Combating Aging with the Colt Duty Cycle Equalizer
Bias temperature instability, hot-carrier injection, and gate-oxide wearout will cause severe lifetime degradation in the performance and the reliability of future CMOS devices. Th...
Erika Gunadi, Abhishek A. Sinkar, Nam Sung Kim, Mi...
JCP
2007
154views more  JCP 2007»
13 years 8 months ago
Partially Reconfigurable Vector Processor for Embedded Applications
—Embedded systems normally involve a combination of hardware and software resources designed to perform dedicated tasks. Such systems have widely crept into industrial control, a...
Muhammad Z. Hasan, Sotirios G. Ziavras