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ISLPED
2003
ACM
90views Hardware» more  ISLPED 2003»
14 years 1 months ago
Understanding and minimizing ground bounce during mode transition of power gating structures
We introduce and analyze the ground bounce due to power mode transition in power gating structures. To reduce the ground bounce, we propose novel power gating structures in which ...
Suhwan Kim, Stephen V. Kosonocky, Daniel R. Knebel
ICCAD
2007
IEEE
130views Hardware» more  ICCAD 2007»
14 years 5 months ago
Analysis and optimization of power-gated ICs with multiple power gating configurations
- Power gating is an efficient technique for reducing leakage power in electronic devices by disconnecting blocks idle for long periods of time from the power supply. Disconnecting...
Aida Todri, Malgorzata Marek-Sadowska, Shih-Chieh ...
SAMOS
2007
Springer
14 years 2 months ago
Automated Power Gating of Registers Using CoDeL and FSM Branch Prediction
In this paper, we use the CoDeL hardware design platform to analyze the potential and performance impact of power gating individual registers. For each register, we examine the per...
Nainesh Agarwal, Nikitas J. Dimopoulos
ICCAD
2009
IEEE
93views Hardware» more  ICCAD 2009»
13 years 6 months ago
An efficient wakeup scheduling considering resource constraint for sensor-based power gating designs
Power gating has been a very effective way to reduce leakage power. One important design issue for a power gating design is to limit the surge current during the wakeup process. N...
Ming-Chao Lee, Yu-Ting Chen, Yo-Tzu Cheng, Shih-Ch...
JCO
2011
115views more  JCO 2011»
13 years 3 months ago
Approximation scheme for restricted discrete gate sizing targeting delay minimization
Discrete gate sizing is a critical optimization in VLSI circuit design. Given a set of available gate sizes, discrete gate sizing problem asks to assign a size to each gate such th...
Chen Liao, Shiyan Hu