264 search results - page 8 / 53 » Timing driven power gating |
ISCAS
2008
IEEE
14 years 3 months ago
2008
IEEE
Abstract— Existing methods of gate level power attack countermeasures depend on exact capacitance matching of the dual-rail data outputs of each gate. Process variability and a l...
ISVLSI
2007
IEEE
14 years 2 months ago
2007
IEEE
— We present a performance analysis of CoDeL, a highly efficient automated clock gating platform for rapidly developing power efficient hardware architectures. It automatically...
DAC
2005
ACM
13 years 10 months ago
2005
ACM
Minimizing power consumption is one of the most important objectives in IC design. Resizing gates and assigning different Vt’s are common ways to meet power and timing budgets. ...
HPCA
2003
IEEE
14 years 9 months ago
2003
IEEE
With the scaling of technology and the need for higher performance and more functionality, power dissipation is becoming a major bottleneck for microprocessor designs. Pipeline ba...
DAC
2005
ACM
14 years 9 months ago
2005
ACM
Abstract-- Network processors (NPs) have emerged as successful platforms to providing both high performance and flexibility in building powerful routers. Typical NPs incorporate mu...