Leakage current is a key factor in IC power consumption even in the active operating mode. We investigate the simultaneous optimization of gate size and threshold voltage to reduc...
— Structural transformation of a design to enhance its testability while satisfying design constraints on power and performance, can result in improved test cost and test confid...
— Run-time Active Leakage Reduction (RALR) is a recent technique and aims at aggressively reducing leakage power consumption. This paper studies the feasibility of RALR from the ...
Abstract— This paper presents a post-route, timingconstrained gate-sizing algorithm for crosstalk reduction. Gate-sizing has emerged as a practical and feasible method to reduce ...
Abstract--Technology scaling in the nanometer era has increased the transistor's susceptibility to process variations. The effects of such variations are having a huge impact ...
Venkataraman Mahalingam, N. Ranganathan, J. E. Har...