4164 search results - page 19 / 833 » Timing model reduction for hierarchical timing analysis |
ALMOB
2008
13 years 9 months ago
2008
Background: It is of biological interest to make genome-wide predictions of the locations of DNA melting bubbles using statistical mechanics models. Computationally, this poses th...
ICIP
2006
IEEE
14 years 10 months ago
2006
IEEE
This paper seeks to increase the efficiency of background subtraction algorithms for motion detection. Our method uses a quadtree-base hierarchical framework that samples a small ...
RTCSA
2008
IEEE
14 years 3 months ago
2008
IEEE
DNA
2004
Springer
14 years 2 months ago
2004
Springer
Abstract. Speed of computation and power consumption are the two main parameters of conventional computing devices implemented in microelectronic circuits. As performance of such d...
ICCAD
2009
IEEE
13 years 6 months ago
2009
IEEE
Double patterning lithography (DPL) is a likely resolution enhancement technique for IC production in 32nm and below technology nodes. However, DPL gives rise to two independent, ...