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GAMEON
2007
13 years 10 months ago
Opponent Modeling in Real-Time Strategy Games
Real-time strategy games present an environment in which game AI is expected to behave realistically. One feature of realistic behaviour in game AI is the ability to recognise the...
Frederik Schadd, Sander Bakkes, Pieter Spronck
EURODAC
1994
IEEE
138views VHDL» more  EURODAC 1994»
14 years 1 months ago
A VHDL-based bus model for multi-PCB system design
In the development of bus-based systems and individual PCB boards interfacing to a bus, the simulation usually requires a specific test bench or creation of quite complex stimuli....
Jari Toivanen, Jari Honkola, Jari Nurmi, Jyrki Tuo...
DAC
2007
ACM
14 years 10 months ago
Modeling the Function Cache for Worst-Case Execution Time Analysis
Static worst-case execution time (WCET) analysis is done by modeling the hardware behavior. In this paper we describe a WCET analysis technique to analyze systems with function ca...
Raimund Kirner, Martin Schoeberl
DAC
1995
ACM
14 years 17 days ago
Automatic Clock Abstraction from Sequential Circuits
Our goal is to transform a low-level circuit design into a more representation. A pre-existing tool, Tranalyze [4], takes a switch-level circuit and generates a functionally equiv...
Samir Jain, Randal E. Bryant, Alok Jain
WSC
2008
13 years 11 months ago
Simplification and aggregation strategies applied for factory analysis in conceptual phase using simulation
Despite that simulation possesses an establish background and offers tremendous promise for designing and analyzing complex production systems, manufacturing industry has been les...
Matias Urenda Moris, Amos Ng, Jacob Svensson