51 search results - page 9 / 11 » Timing variation-aware high-level synthesis |
IJVR
2006
13 years 7 months ago
2006
In this paper, we will present an overview of existing research in the vast area of IVH systems. We will also present our ongoing work on improving the expressive capabilities of I...
DATE
2007
IEEE
14 years 1 months ago
2007
IEEE
Design closure becomes hard to achieve at physical layout stage due to the emergence of long global interconnects. Consequently, interconnect planning needs to be integrated in hi...
SIES
2007
IEEE
14 years 1 months ago
2007
IEEE
— High level synthesis is one of the next major steps to improve the hw/sw co-design process. The advantages of high nthesis are two-fold. At first the level of abstraction is r...
RSP
2006
IEEE
14 years 1 months ago
2006
IEEE
In a hardware-software co-design environment, an application is partitioned into modules. Each module is then mapped either to software or to hardware. The mapping process is driv...
VLSID
2003
IEEE
14 years 7 months ago
2003
IEEE
Design of efficient System-on-Chips (SoCs) require thorough application analysis to identify various compute intensive parts. These compute intensive parts can be mapped to hardwa...