188 search results - page 13 / 38 » Timing-driven optimization using lookahead logic circuits |
WEA
2010
Springer
14 years 4 months ago
2010
Springer
Abstract. A new technique for combinational logic optimization is described. The technique is a two-step process. In the first step, the nonlinearity of a circuit – as measured ...
GECCO
2006
Springer
14 years 1 months ago
2006
Springer
Genetic Parallel Programming (GPP) is a novel Genetic Programming paradigm. Based on the GPP paradigm and a local search operator - FlowMap, a logic circuit synthesizing system in...
JUCS
2007
13 years 10 months ago
2007
: This article presents an architecture that encrypts data with the AES algorithm. This architecture can be implemented on the Xilinx Virtex II FPGA family, by applying pipelining ...
TCAD
2002
13 years 9 months ago
2002
In this paper, we propose a new approach for VLSI interconnect global routing that can optimize both congestion and delay, which are often competing objectives. Our approach provi...
ISPD
1999
ACM
14 years 2 months ago
1999
ACM
For the development and evaluation of CAD-tools for partitioning, floorplanning, placement, and routing of digital circuits, a huge amount of benchmark circuits with suitable cha...