188 search results - page 14 / 38 » Timing-driven optimization using lookahead logic circuits |
DAC
1995
ACM
14 years 1 months ago
1995
ACM
Abstract—With delays due to the physical interconnect dominating the overall logic path delays, circuit-level delay optimization must take interconnect effects into account. Inst...
GECCO
2005
Springer
2005
Springer
Providing information from the environment for growing electronic circuits through polymorphic gates
14 years 3 months ago
This paper deals with the evolutionary design of programs (constructors) that are able to create (n+2)-input circuits from n-input circuits. The growing circuits are composed of p...
PATMOS
2005
Springer
14 years 3 months ago
2005
Springer
This paper presents a modular optimization framework for custom digital circuits in the power – performance space. The method uses a static timer and a nonlinear optimizer to max...
ICCAD
1998
IEEE
14 years 2 months ago
1998
IEEE
Noise can cause digital circuits to switch incorrectly and thus produce spurious results. Noise can also have adverse power, timing and reliability e ects. Dynamic logic is partic...
GECCO
2005
Springer
14 years 3 months ago
2005
Springer
Instead of having fixed px and pm, this paper presents the use of fuzzy logic to adaptively tune px and pm for optimization of power electronic circuits throughout the process. By...