Sciweavers

188 search results - page 36 / 38
» Timing-driven optimization using lookahead logic circuits
Sort
View
ASPDAC
2007
ACM
129views Hardware» more  ASPDAC 2007»
13 years 11 months ago
ECO-system: Embracing the Change in Placement
In a realistic design flow, circuit and system optimizations must interact with physical aspects of the design. For example, improvements in timing and power may require replacing ...
Jarrod A. Roy, Igor L. Markov
FCCM
2007
IEEE
165views VLSI» more  FCCM 2007»
13 years 8 months ago
Sparse Matrix-Vector Multiplication Design on FPGAs
Creating a high throughput sparse matrix vector multiplication (SpMxV) implementation depends on a balanced system design. In this paper, we introduce the innovative SpMxV Solver ...
Junqing Sun, Gregory D. Peterson, Olaf O. Storaasl...
SLIP
2003
ACM
14 years 7 days ago
Error-correction and crosstalk avoidance in DSM busses
Aggressive process scaling and increasing clock rates have made crosstalk noise an important issue in VLSI design. Switching on adjacent wires on long bus lines can increase delay...
Ketan N. Patel, Igor L. Markov
DAC
2008
ACM
14 years 8 months ago
Automated transistor sizing for FPGA architecture exploration
The creation of an FPGA requires extensive transistor-level design. This is necessary for both the final design, and during architecture exploration, when many different logic and...
Ian Kuon, Jonathan Rose
HEURISTICS
2002
99views more  HEURISTICS 2002»
13 years 6 months ago
Parallelizing Tabu Search on a Cluster of Heterogeneous Workstations
In this paper, we present the parallelization of tabu search on a network of workstations using PVM. Two parallelization strategies are integrated: functional decomposition strate...
Ahmad A. Al-Yamani, Sadiq M. Sait, Habib Youssef, ...