Booth encoding is believed to yield faster multiplier designs with higher energy consumption. 16x16-bit Booth and NonBooth multipliers are analyzed in energy and delay space under...
In this paper, we describe a low power and high speed multiplier suitable for standard cell-based ASIC design methodologies. For the purpose, an optimized booth encoder, compact 2...
Ki-seon Cho, Jong-on Park, Jin-seok Hong, Goang-se...
One of the main reasons for using asynchronous design is that it offers the opportunity to exploit the datadependent latency of many operations in order to achieve low-power, high...
Aristides Efthymiou, W. Suntiamorntut, Jim D. Gars...