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SBCCI
2003
ACM

94views VLSI» more SBCCI 2003»

A New Pipelined Array Architecture for Signed Multiplication

14 years 25 days ago

Download www.inesc-id.pt

– We present a new architecture for signed multiplication which maintains the pure form of an array multiplier, exhibiting a much lower overhead than the Booth architecture. This...

Eduardo A. C. da Costa, Sergio Bampi, José ...

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ICCD
2001
IEEE

144views Hardware» more ICCD 2001»

An Area-Efficient Iterative Modified-Booth Multiplier Based on Self-Timed Clocking

14 years 4 months ago

Download ics.kaist.ac.kr

A new iterative multiplier based on a self-timed clocking scheme is presented. To reduce the area required for the multiplier, only two CSA rows are iteratively used to complete a...

Myoung-Cheol Shin, Se-Hyeon Kang, In-Cheol Park

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ISLPED
1997
ACM

85views Hardware» more ISLPED 1997»

A new 4-2 adder and booth selector for low power MAC unit

13 years 11 months ago