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DAC
2007
ACM
16 years 3 months ago
Modeling the Function Cache for Worst-Case Execution Time Analysis
Static worst-case execution time (WCET) analysis is done by modeling the hardware behavior. In this paper we describe a WCET analysis technique to analyze systems with function ca...
Raimund Kirner, Martin Schoeberl
FPGA
2000
ACM
122views FPGA» more  FPGA 2000»
15 years 6 months ago
A reconfigurable multi-function computing cache architecture
A considerable portion of a chip is dedicated to a cache memory in a modern microprocessor chip. However, some applications may not actively need all the cache storage, especially...
Huesung Kim, Arun K. Somani, Akhilesh Tyagi
TC
2008
15 years 2 months ago
Counter-Based Cache Replacement and Bypassing Algorithms
Recent studies have shown that, in highly associative caches, the performance gap between the Least Recently Used (LRU) and the theoretical optimal replacement algorithms is large,...
Mazen Kharbutli, Yan Solihin
CF
2005
ACM
15 years 4 months ago
Drowsy region-based caches: minimizing both dynamic and static power dissipation
Power consumption within the memory hierarchy grows in importance as on-chip data caches occupy increasingly greater die area. Among dynamic power conservation schemes, horizontal...
Michael J. Geiger, Sally A. McKee, Gary S. Tyson
CF
2007
ACM
15 years 6 months ago
Performance/area efficiency in chip multiprocessors with micro-caches
This paper proposes the use of very small instruction caches, called micro-caches (
Michela Becchi, Mark A. Franklin, Patrick Crowley