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131
Voted
DSD
2010
IEEE
161views Hardware» more  DSD 2010»
15 years 2 months ago
Design of Trace-Based Split Array Caches for Embedded Applications
—Since many embedded systems execute a predefined set of programs, tuning system components to application programs and data is the approach chosen by many design techniques to o...
Alice M. Tokarnia, Marina Tachibana
119
Voted
AMAST
2008
Springer
15 years 4 months ago
The Verification of the On-Chip COMA Cache Coherence Protocol
This paper gives a correctness proof for the on-chip COMA cache coherence protocol that supports the Microgrid of microtheaded architecture, a multi-core architecture capable of in...
Thuy Duong Vu, Li Zhang, Chris R. Jesshope
ICCS
2005
Springer
15 years 8 months ago
Investigation of Cache Coherence Strategies in a Mobile Client/Server Environment
In this article, we present an investigation case study based on an implementation and performance analysis of three different cache coherence strategies over a real wireless envi...
Carla Diacui Medeiros Berkenbrock, Mario A. R. Dan...
118
Voted
IEEEPACT
2007
IEEE
15 years 9 months ago
L1 Cache Filtering Through Random Selection of Memory References
Distinguishing transient blocks from frequently used blocks enables servicing references to transient blocks from a small fully-associative auxiliary cache structure. By inserting...
Yoav Etsion, Dror G. Feitelson
111
Voted
ISLPED
1995
ACM
95views Hardware» more  ISLPED 1995»
15 years 6 months ago
Reducing the frequency of tag compares for low power I-cache design
In current processors, the cache controller, which contains the cache directory and other logic such as tag comparators, is active for each instruction fetch and is responsible fo...
Ramesh Panwar, David A. Rennels