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» Tolerance Models in Hardware Description Languages
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MEMOCODE
2007
IEEE
14 years 1 months ago
Scheduling as Rule Composition
Bluespec is a high-level hardware description language used for architectural exploration, hardware modeling and synthesis of semiconductor chips. In Bluespec, one views hardware ...
Nirav Dave, Arvind, Michael Pellauer
DAC
2003
ACM
14 years 22 days ago
A timing-accurate modeling and simulation environment for networked embedded systems
The design of state-of-the-art, complex embedded systems requires the capability of modeling and simulating the complex networked environment in which such systems operate. This i...
Franco Fummi, Giovanni Perbellini, Paolo Gallo, Ma...
DAC
1998
ACM
14 years 8 months ago
Functional Vector Generation for HDL Models Using Linear Programming and 3-Satisfiability
Abstract-Our strategy for automatic generation of functional vectors is based on exercising selected paths in the given hardware description language (HDL) model. The HDL model des...
Farzan Fallah, Srinivas Devadas, Kurt Keutzer
BMAS
2000
IEEE
13 years 12 months ago
Verilog-AMS: Mixed-Signal Simulation and Cross Domain Connect Modules
Verilog-AMS is one of the major mixed-signal hardware description languages on today’s market. In addition to the extended capabilities to model analog and digital behavior, the...
Peter Frey, Donald O'Riordan
WSC
1998
13 years 8 months ago
SEAMS: Simulation Environment for VHDL-AMS
VHDL-AMS is an Analog and Mixed-Signal extension to the Very High Speed Integrated Circuit Hardware Description Language (VHDL). With the standardization of VHDL-AMS, capable and ...
Peter Frey, Kathiresan Nellayappan, Vasudevan Sahn...