134 search results - page 4 / 27 » Tolerance Models in Hardware Description Languages |
FCCM
1995
IEEE
13 years 11 months ago
1995
IEEE
FPGA-based synthesis tools require information about behaviour and architectural to make effective use of the limited number of cells typically available. A hardware description l...
VLSID
1999
IEEE
13 years 11 months ago
1999
IEEE
In hardware - software codesign paradigm often a performance estimation of the system is needed for hardware - software partitioning. The tremendous growth of application specific...
DATE
2008
IEEE
14 years 1 months ago
2008
IEEE
This paper describes an implementation language and synthesis system for automatically generating latency insensitive synchronous digital designs. These designs decouple behaviora...
ACSD
2009
IEEE
14 years 2 months ago
2009
IEEE
We present a formal semantics for a subset of Verilog, commonly used to describe cell libraries, in terms of transition systems. Such transition systems can serve as input to symb...
SIGIR
2003
ACM
14 years 21 days ago
2003
ACM
A novel Hardware Assisted Top-Doc (HAT) component is disclosed. HAT is an optimized content indexing device based on a modified inverted index structure. HAT accommodates patterns...