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» Tolerance Models in Hardware Description Languages
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MICRO
1996
IEEE
106views Hardware» more  MICRO 1996»
14 years 24 days ago
Optimization of Machine Descriptions for Efficient Use
A machine description facility allows compiler writers to specify machine execution constraints to the optimization and scheduling phases of an instruction-level parallelism (ILP)...
John C. Gyllenhaal, Wen-mei W. Hwu, B. Ramakrishna...
ESOP
2010
Springer
14 years 6 months ago
Faulty Logic: Reasoning about Fault Tolerant Programs
Transient faults are single-shot hardware errors caused by high energy particles from space, manufacturing defects, overheating, and other sources. Such faults can be devastating f...
Matthew L. Meola and David Walker
CASES
2007
ACM
14 years 19 days ago
Compiler generation from structural architecture descriptions
With increasing complexity of modern embedded systems, the availability of highly optimizing compilers becomes more and more important. At the same time, application specific inst...
Florian Brandner, Dietmar Ebner, Andreas Krall
SAC
2005
ACM
14 years 2 months ago
An agent model for fault-tolerant systems
This paper describes the use of fault tolerance in a multiagent system. Such an approach is based on the modeling of autonomous agents with planning capabilities. These capabiliti...
Avelino F. Zorzo, Felipe Rech Meneguzzi
ETFA
2006
IEEE
14 years 2 months ago
Empirical Evaluation of SysML through the Modeling of an Industrial Automation Unit
Industrial automation systems may include people, hardware, software and others necessaries to produce the desirable results. The SysML modeling language is being proposed, by OMG...
Marcos Vinicius Linhares, Alexandre Jose da Silva,...