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MICRO
1998
IEEE
89views Hardware» more  MICRO 1998»
13 years 11 months ago
Load Latency Tolerance in Dynamically Scheduled Processors
This paper provides quantitative measurements of load latency tolerance in a dynamically scheduled processor. To determine the latency tolerance of each memory load operation, our...
Srikanth T. Srinivasan, Alvin R. Lebeck
ICPP
1995
IEEE
13 years 10 months ago
Hiding Miss Latencies with Multithreading on the Data Diffusion Machine
— Large parallel computers require techniques to tolerate the potentially large latencies of accessing remote data. Multithreadingis onesuch technique. We extend previous studies...
Henk L. Muller, Paul W. A. Stallard, David H. D. W...
ISCA
2003
IEEE
101views Hardware» more  ISCA 2003»
14 years 8 days ago
Overcoming the Limitations of Conventional Vector Processors
Despite their superior performance for multimedia applications, vector processors have three limitations that hinder their widespread acceptance. First, the complexity and size of...
Christoforos E. Kozyrakis, David A. Patterson
EDBT
2006
ACM
156views Database» more  EDBT 2006»
13 years 10 months ago
FlexInd: A Flexible and Parameterizable Air-Indexing Scheme for Data Broadcast Systems
Abstract. In wireless data broadcast systems, popular information is repetitively disseminated through possibly multiple communication channels to mobile clients using various type...
André Seifert, Jen-Jou Hung
ISCA
2010
IEEE
185views Hardware» more  ISCA 2010»
14 years 2 days ago
Dynamic warp subdivision for integrated branch and memory divergence tolerance
SIMD organizations amortize the area and power of fetch, decode, and issue logic across multiple processing units in order to maximize throughput for a given area and power budget...
Jiayuan Meng, David Tarjan, Kevin Skadron